This invention relates to high-density electronic modules, which are intended to meet the apparently insatiable desire for incorporating more electronic capacity in a given space, or reducing the space required for a given amount of electronic capacity.
One of the primary uses of the present invention is to provide memory modules for use in computer apparatus. However, the same concepts may be applied to any field where high-density of electronic circuitry is desired.
To a significant extent, the background of this invention is provided by patented (or applied for) inventions assigned to the assignee of this application. Those inventions relate to the stacking and laminating of multiple chips, or substrates, each carrying integrated circuitry (IC). The stacked chips provide a module having a multiplicity of electrical leads exposed on at least one access plane of the module, the planes in which the chips extend being perpendicular to the access plane.
In U.S. Pat. No. 4,551,629, issued Nov. 5, 1985, the modules of stacked chips are intended to be used in conjunction with photodetectors, which are secured to one access plane of the module, and which comprise a dense array of radiation/electronic transducers.
In U.S. Pat. No. 4,525,921, issued July 2, 1985, similar modules, comprising stacked, circuit-carrying chips, are intended for general use, including the computer memory components mentioned above.
The present invention is intended to solve problems involved in creating easily handled, reliable components for use as computer memories, control logic, arithmetic units, processors, and the like. It also is intended to solve problems resulting from extreme heat dissipation needs created by densely packed electronic chips, particularly where the chip material is an inefficient heat conductor.
Application Ser. No. 856,835, filed Apr. 25, 1986 by the same inventor as the present application, which issued as U.S. Pat. No. 4,706,166 on Nov. 10, 1988 discloses an electronic package comprising a module of stacked (laminated) IC chips which is supported on a stack-supporting substrate, with its access (electrical interconnection) plane resting directly on that substrate. Aligned bonding bumps on the access plane of the stack and on the stack-supporting substrate are integrated to provide a multiplicity of separate electrical conductive paths.
Inadequate heat dissipation is a problem encountered if the stacked chips are not effective thermal conductors and/or if the stacked chips have particularly high power requirements. This problem may not be encountered with stacked silicon chips, but it will occur with stacks of such chips as gallium arsenide (GaAs), silicon-on-sapphire (SOS), or silicon-on-insulator (SOI).